The present invention relates generally to a low power analog-to-digital convertor for converting analog signals to digital values. More particularly, the present invention relates to an analog-to-digital convertor comprising part of a waveform storage circuit for use in low power applications, such as use in an implantable medical device. Still more particularly, the present invention relates to an analog-to-digital circuit with the ability to predict the digital conversion value based upon previously converted analog signals, and which selects a conversion technique depending upon the accuracy of the prediction.
Disruption of natural pacemaking capabilities of the heart as a result of aging or disease commonly is treated by the insertion into a patient of an artificial cardiac pacing device, commonly referred to as a pacemaker. A pacemaker provides rhythmic electrical discharges that are applied to the heart at a desired rate from the implanted artificial pacemaker. In its simplest form, the pacemaker consists of a pulse generator powered by a self-contained battery pack, and a lead including at least one stimulating electrode(s) for delivery of electrical impulses to excitable myocardial tissue in the appropriate chamber(s) in the right side of the patient's heart. In some instances, epicardial electrodes are implanted by surgically splitting the patient's chest or according to other well known techniques, and suturing or screwing them in to the epicardium. Typically, the pulse generator is surgically implanted in a subcutaneous pouch in the patient's chest. In operation, the electrical stimuli are delivered to the excitable cardiac tissue via an electrical circuit that includes the stimulating and reference electrodes, and the body tissue and fluids.
Pacemakers range from the simple fixed rate device that provides pacing with no sensing function, to highly complex models implemented to provide fully automatic dual chamber pacing and sensing functions. The latter type of pacemaker is the latest in a progression toward psychologic pacing; that is, the mode of artificial pacing that restores cardiac function as much as possible toward natural pacing.
Typically, and as shown in FIG. 1, an implantable medical device 12, such as a pacemaker, for example, comprises electrical circuits that are controlled by processing circuitry 26, such as a central processing unit (CPU) or microprocessor. Because of the implementation of the microprocessor in the pacemaker or other implantable device, the pacemaker can be programmed by a physician through an external device 10 to customize the operation of the device to the patient's conditions. As shown in FIG. 1, the pacemaker or other implantable device 12 includes a coil antenna 30 which is capable of communicating through electromagnetic waves to a coil antenna 24 in the external programmer/reader 20 in the external device 10. The pacemaker can be programmed after it is implanted in the patient 14 through electromagnetic signals transmitted by the external programmer. The pacemaker 12 attaches to the patient's heart 16 through electrical leads 18. The pacemaker also includes a communications interface 28 to transmit and receive signals through an antenna 30. Similarly, the external device 10 also includes a communications interface 22 connected to antenna 24.
The pacemaker circuitry typically is powered by a battery pack 32 that is surgically implanted at the same time as the pacemaker. When the battery pack 32 reaches the end of its useful life, it must be either replaced or recharged. If the battery pack 32 must be replaced, another surgical procedure is necessary to make the replacement. Power consumption of pacemaker circuitry, therefore, is critical.
In addition to the microprocessor, the pacemaker also may include a memory device 35, such as random access memory (RAM) chips, for storing signals indicative of the patient's health. The pacemaker may have the capability of monitoring physiological parameters of the patient, such as electrocardiogram (or EKG) signals, and may store digital signals representative of these parameters in the memory device 35. When prompted by the external device, the processing circuitry 26 can transmit the contents of the memory device 35 to the external programmer/reader 20 for analysis by the physician. According to conventional digital processing techniques, a clock signal is provided by an internal clock 36 which synchronizes the activities of the processing circuitry 26 and memory 35.
The conversion of electrical analog signals (electrograms), such as EKG signals, into digital values for storage in memory raises concerns regarding power consumption, accuracy and timeliness associated with the conversion process. A conventional architecture for an analog-to-digital convertor (or ADC) is shown for purposes of illustration in FIG. 2. The ADC of FIG. 2 includes a code generator device with a digital-to-analog converter (DAC), followed by a comparator that compares the output of the DAC with the analog voltage signal obtained from a sample and hold circuit. The analog-to-digital conversion is performed according to conventional techniques by driving different digital codes into the DAC until the resulting DAC output is approximately equal to the analog voltage to be digitized. At that time, an ADC output signal, shown as ADC[7:0], is provided as an output of the code generator circuitry. If an eight-bit digital code is used, then 256 coded values (2'=256) are available to encode the electrogram signal.
The most common algorithm for generating the digital codes (which are supplied as inputs to the DAC) is called successive-approximation. Successive-approximation involves a bilinear search for the correct digital code by first setting the most significant digital bit high with all lower bits low, and observing the comparator output to determine whether the analog value is in the lower or upper half of the available code space. If the comparator indicates that the actual analog signal has a magnitude greater than the mid value, then the most significant bit is indicated as a digital "1". Conversely, if the actual analog signal has a magnitude less than the mid value, then the most significant bit is indicated as a digital "0".
The successive-approximation algorithm is repeated on each successive bit to determine whether that bit should be assigned a value of "0" or "1". The process therefore is performed once for each bit of the desired digital code width, so that if an eight bit digital code is available, the successive-approximation method is repeated eight times (once each dock cycle) to determine the value of the digital code. Example of successive-approximation ADC's are illustrated in U.S. Pat. Nos. 5,017,920, 5,028,926, 5,057,841, 5,206,650, 5,144,310, 5,262,779. Successive approximation ADC's are typically used in implantable medical devices.
An alternative algorithm that can be used to generate the digital code input to the DAC involves a linear search for the best digital representation of the analog value. This linear search algorithm starts at either the minimum or maximum digital code value and either increments or decrements the digital value once each dock cycle until the comparator output changes state, thus indicating that the correct digital representation of the analog signal has been reached. This type of linear searching for the digital representation of the analog signal provides a much slower conversion time than the successive-approximation technique unless the correct digital code is near the starting digital value used by the linear search algorithm. For an eight bit digital code space, the linear search algorithm can take anywhere from 1 attempt to 255 attempts to determine the proper digital representation of the analog signal.
The vast majority of the power consumed by the ADC shown in FIG. 2 may be attributed to the quiescent bias current of the comparator. Consequently, the average power consumed for each analog-to-digital conversion can be reduced significantly by reducing the number of operations or comparisons performed by the ADC, and thus the amount of time the comparator must remain enabled. It is an object of the present invention to develop an ADC that optimizes the code generation of FIG. 2 to minimize the number of clock cycles necessary to perform the digital conversion of the analog signal.
While the benefits of such an ADC are apparent, particularly in low power applications such as an implantable medical device, to date no such power saving ADC has been developed.